1. Field of the Invention
The invention relates to an electrical circuit timing and verification system, and particularly to a computer-based system that automates and facilitates the entry, modification, analysis and generation of test benches in multiple HDL digital hardware designs via a unique wavetable spreadsheet interface which simultaneously displays data as both waveforms and numerical cell values.
2. Description of Related Art
Hardware Description Languages (HDLs) are language specifications for precisely describing the behavior and programming the function of electrical circuits. Test benches are HDL descriptions specialized in describing and verifying the behavior of electrical circuits.
Events and data in electrical circuits are routinely described by signals (one bit wide), and vectors (two or more bits wide). The manner in which signals and vectors change as time flows are described by displaying signal snapshots sequentially. The resulting object is called a waveform.
If signal waveforms are not properly synchronized, the electrical circuit may not behave as intended, and consequently generate unwanted operational errors.
When a circuit is built, an engineer will use timing verification techniques to identify such errors such that they can be eliminated.
One popular timing verification technique is the creation of timing waveforms to describe the logical relationships, values, and timing constraints among the signals in a given electrical circuit.
A technique for testing the behavior of electrical circuits under arbitrary and specific input data streams are also needed to detect data sensitive errors. Spreadsheet-based tables of signal data streams stacked on top of each other are commonly used to spot data-sensitive errors. However, because table-based descriptions of data lacks visual content, it is inherently ill suited to convey the logical relationship among the same data. These tables are usually generated manually via programming scripts of varying complexity.
HDL simulators are typically used to test and visualize all the various logical and physical conditions that will influence the behavior and proper function of an electrical circuit.
A problem with simulators is that they cannot be used until the behavioral description of the design has been properly and manually encoded as a script or as an HDL test bench description. This in itself is an error-prone and tedious process.
Likewise, HDL test bench descriptions of test pattern data are, by themselves, static, thereby requiring considerable effort to modify in response to changes in the underlying electrical circuit specification.
Another problem with traditional simulators is that, once a problem is encountered, the test pattern must be modified manually in order to keep it up to date.
Thus, it is highly desirable to create a xe2x80x9cseamlessxe2x80x9d two-way link between the HDL description of the electrical circuit, and the test pattern used to verify it.
Furthermore, in a truly seamless test environment, changes in the specification of the circuit interface to the outside world would have to be automatically reflected in the test pattern itself. Were this not the case, any HDL test bench description generated from the test pattern would no longer correctly reflect the user""s intent.
Because HDL test benches are the standard format used by engineers to test designs with HDL simulators, there is a need for automating their entry, modification, and generation, resulting in HDL descriptions that are both quantitatively and qualitatively correct.
The present invention also addresses the problem which arises when an HDL design (VHDL or VERILOG(copyright), or other HDLs) is synthesized to a HDL netlist and the resulting netlist may not be compatible with test benches created for the pre-synthesis HDL source. The most common reasons for this are:
1) Unused inputs are optimized out during synthesis, and therefore not present in the port list;
2) A signal is defined as bi-directional (inout, buffer) in the HDL source, but is used only as an output. Synthesis correctly recognizes the signal is uni-directional and changes the port mode from bi-directional to uni-directional;
3) Complex data types are remapped to synthesized types. An example is in VHDL the INTEGER data type is remapped to std_logic_vector; or
4) Parameters (VERILOG(copyright)) and Generics (VHDL) are used pre-synthesis to set up the design. Once synthesized, these are dropped from the port definition. Pre-synthesis test benches must instantiate the design using the parameter for it to function as intended. Post-synthesis designs have been flattened, and no parameters remain in the ports; or
5) Partially used vectors (those with some unused bits) are changed in width; or
6) The order of signals in the port is changed, thereby causing test benches which rely on port order for instantiation to be incompatible.
The net result is that the test engineer needs to modify all test benches to accommodate to the changes. The designer needs to update all port definitions, component instantiations, signal assignments, and output assertions. Each time changes are made to the pre-synthesis design (then synthesized) the test benches need to be re-updated to maintain consistency.
For example, pre-synthesis VHDL definition for a counter might look like the following:
After synthesis, the VHDL netlist ports look like this:
Notice the last item (COUNT) in the pre-synthesis definition is:
COUNT: inout integer range 0 to 7:=0
In this case the counter is of mode xe2x80x9cinoutxe2x80x9d and is of type xe2x80x9cintegerxe2x80x9d.
After synthesis it becomes:
COUNT: out STD_LOGIC_VECTOR (2 downto 0)
Notice the mode is now xe2x80x9coutxe2x80x9d and the type is xe2x80x9cstd_logic_vectorxe2x80x9d.
The changes made during synthesis render the pre-synthesis (behavioral) test benches unusable without modification. Normally the test benches must be updated by hand. All ports must be updated to match the synthesized netlist. Generics (and parameters) must be eliminated. Unused signals must be stripped from the port and the test bench. The test bench code must then be revised, changing all input assignments, check procedures, file IO and other portions of the test bench which are affected by signal definition changes and port changes.
During simulation and synthesis of behavioral designs, attributes are passed to the unit under test via generics or parameters. These attributes can be changed in the behavioral description. The last value assumed by the generics must be used during the remap process to ensure continuity between behavioral and post-synthesis testing.
One solution to this problem is to restrict the HDL constructs used in a design. For example, allowing only std_logic_vectors in place of integers might eliminate data type remapping. Port mode changes can be resolved (manually) by back annotating the synthesized port modes into the original behavioral HDL source. While these solutions reduce the occurrences of port map problems, they do not eliminate them.
The present invention addresses this problem by including an Automatic Post Synthesis Test Bench Remap feature that automatically re-maps signals based upon their name, mode and data type.
A computer-based system, which automates and facilitates the entry, modification, analysis and generation of HDL test benches from standard HDL description code.
The present invention utilizes a unique combined waveform- and table data entry system to facilitate fast behavioral verification of digital hardware circuit designs. A cell based, tabular data entry system consists of rows of signal names and columns of cell values containing time-varying data, which are displayed as waveforms.
The present invention allows the user to enter data in a way similar to data entry in standard spreadsheets, as well as editing values by the use of a click event. The data values are represented by both waveforms and cell values, which are shown using dynamic text compression to reduce the viewing space required to see the values. Redundant values are hidden, and constant values are maintained until another value is assigned.
Each cell is partitioned into two distinct phases, input and output. Data entered for a particular signal is automatically entered into the correct portion of the column, automatically setting up the correct timing. Bi-directional signals are allowed two entries per column, one input entry and one output entry. To clarify each column""s time relevance, a color-coding scheme is used. Light blue represents input cells while yellow is used to represent output cells. Gray represents disabled times. An attempt to toggle bits or invoke the invention""s cell editor in a disabled time region automatically makes the change in the preceding active time cell, guaranteeing correct entry 100% of the time.
The system and method of the present invention are for use with arbitrary HDL source code descriptions of electrical circuits and with external HDL simulators. The system comprises: (1) an HDL input editor, for dynamically retrieving, viewing and modifying arbitrary HDL descriptions of electrical circuits; (2) a scanning interface, which retrieves specific circuit sub-components to test (unit under test, or UUT) from arbitrary HDL descriptions; (3) a time scaling unit, which specifies basic timing parameters that must be met during normal circuit operation; (4) a wavetable editor, for dynamically viewing, creating and modifying test patterns; (5) a wavetable-to-test bench translation unit, which generates HDL behavioral descriptions (test benches) of the test pattern in the wavetable unit; (6) a back annotation unit which updates waveforms with simulation results, or highlights simulation errors; and (7) a remap unit which updates the waveforms upon source HDL port changes or reassociation with post-synthesis source HDL.
The Wavetable editor seamlessly blends waveform signals, pattern data and the interface specified by the underlying HDL description. Waveform signals can be altered at specific points in time simply by clicking on their background cells, or through regions of arbitrary size through a pattern generator.
The HDL Editor and the wavetable Editor contain two-way links, which allows them to maintain consistency and coherency between the test pattern under development and the input/output interface of the UUT.
Similarly, the time scaling unit has a one-way link to the wavetable editor, which allows it to modify the entire test pattern under development so that it conforms to changing requirements for the electrical circuit being tested.
The wavetable-to-test bench translation unit automatically generates HDL test bench specifications fully compatible with most HDL compliant simulators, thereby seamlessly linking arbitrary HDL descriptions of electrical circuits with the simulators needed to test them.
Finally, the back-annotation unit, which takes simulation results and updates the waveforms with the resultant values or highlights mismatches between actual and expected behavior.
The present invention also includes a feature titled, xe2x80x9cChange HDL sourcexe2x80x9d. When a waveform description has been created for a HDL (pre-synthesis) design, the user can simply select the post-synthesis HDL netlist as the new source. The remap unit of the present invention automatically re-maps signals based on their name, mode, and data type. Unused signals are automatically dropped. The waveform can then be re-exported for post-synthesis simulation.
In the examples given above, the signal COUNT is automatically remapped with no user intervention. In the case where there may be possible conflicts, the present invention will ask the user for information such as which signal to re-map to, and how to resolve the new data type. If post-synthesis uses new data types not currently recognized, the remap unit of the present invention will automatically ask for information which will allow it to use the new types and remap the older type correctly.
To summarize, the present invention is a computer system for constructing HDL test benches based upon HDL descriptions of electrical circuits, comprising a means for generating and modifying HDL data descriptions; a computer, including a monitor and memory storage means containing instructions for displaying a spreadsheet comprised of timing waveforms superimposed on an array of cells containing time-varying signal data patterns, wherein the waveforms and the data patterns correspond to the HDL descriptions and are simultaneously displayed on the monitor; means for modifying the waveforms and the signal data patterns; and means for automatically translating the waveforms into a complete HDL test bench file, the test bench file being fully compatible with industry-standard HDL simulators.
In accordance with these and other objects that will become apparent hereinafter, the instant invention will now be described with particular reference to the accompanying drawings.